FUJIWARA Hideo | Nara Institute of Science and Technology (NAIST)

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概要

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著作論文

Design and Optimization of Transparency-Based TAM for SoC Test
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
D-10-18 An Approach to Temperature Control During VLSI Test
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
Program-Based Delay Fault Self-Testing of Processor Cores
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch(Dependable Computing)
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
Effect of BIST Pretest on IC Defect Level(Dependable Computing)
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
Design and Optimization of Transparency-Based TAM for SoC Test

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