Fujiwara Hideo | Nara Institute Of Science And Technology
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概要
関連著者
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Fujiwara Hideo
Nara Institute Of Science And Technology
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Fujiwara Hideo
Naist
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Fujiwara Hideo
The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno
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Fujiwara Hideo
Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)
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Fujiwara H
Nara Inst. Sci. And Technol. Kansai Science City Jpn
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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MASUZAWA Toshimitsu
the Graduate School of Information Science and Technology, Osaka University
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Masuzawa Toshimitsu
Graduate School Of Information Science Nara Institute Of Science And Technology
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Masuzawa Toshimitsu
Nara Institute Of Sciences And Technology
著作論文
- Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
- Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector
- On the Effect of Scheduling in Test Generation
- Testing for the Programming Circuit of SRAM-Based FPGAs
- Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
- A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
- Design for Two-Pattern Testability of Controller-Data Path Circuits
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)