Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis

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概要

• 論文の詳細を見る
• 2003-11-01

著者

• Fujiwara Hideo

  The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno

• Fujiwara Hideo

  Naist

• Fujiwara Hideo

  Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Nara Institute Of Science And Technology

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Fujiwara H

  Nara Inst. Sci. And Technol. Kansai Science City Jpn

• Xiang Dong

  School Of Software Tsinghua University

• GU Shan

  School of Software, Tsinghua University

• Gu Shan

  School Of Software Tsinghua University

関連論文

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• On the Effect of Scheduling in Test Generation
• Testing for the Programming Circuit of SRAM-Based FPGAs
• Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
• Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
• A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
• Design for Two-Pattern Testability of Controller-Data Path Circuits
• Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
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• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
• A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
• Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design

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