Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper we analyze the testability of RTL data paths targeting all detectable path delay faults. The concept of RTL path is introduced. Based on this concept a definition for2-pattern(path delay fault)testable data path is developed. Some necessary and sufficient conditions to support the propagation of 2-pattern vectors for two or more control paths are pointed out. A graph approach of our analysis is also presented.
- 社団法人電子情報通信学会の論文
- 2000-11-23
著者
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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Altaf-ul-amin Md.
Graduate School Of Information Science Nara Institute Of Science And Technology
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Altaf-ui-amin Md.
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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