A Design Scheme for Delay Testing of Controllers Using State Transition Information

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概要

• 論文の詳細を見る

• This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• IWAGAKI Tsuyoshi

  School of Information Science, Japan Advanced Institute of Science and Technology

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• OHTAKE Satoshi

  Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)

• Fujiwara H

  Nara Inst. Of Sci. And Technol. Nara Jpn

• Ohtake Satoshi

  Graduate School Of Information Science Nara Institute Of Science And Technology

• IWAGAKI Tsuyoshi

  Graduate School of Information Science, Nara Institute of Science and Technology

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Iwagaki Tsuyoshi

  Graduate School Of Information Science Japan Advanced Institute Of Science And Technology

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