Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation
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概要
- 論文の詳細を見る
In this paper, a transition test generation method for acyclic sequential circuits is presented. In this method, to generate a test sequence for a transition fault in a given acyclic sequential circuit, constrained combinational stuck-at test generation is performed on its double time-expansion model, which is composed of two copies of a time-expansion model of the given circuit. This method can guarantee complete fault efficiency, i.e., it can generate test sequences for all the testable transition faults and can identify all the untestable transition faults in a given acyclic sequential circuit. Experimental results show that our method can achieve high fault efficiency with drastically short test generation time compared with that obtained by conventional methods.
- 社団法人電子情報通信学会の論文
- 2005-02-11
著者
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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Fujiwara H
Nara Inst. Of Sci. And Technol. Nara Jpn
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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IWAGAKI Tsuyoshi
Graduate School of Information Science, Nara Institute of Science and Technology
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Iwagaki Tsuyoshi
Graduate School Of Information Science Japan Advanced Institute Of Science And Technology
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