Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
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概要
- 論文の詳細を見る
In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the generation of a complete test schedule that efficiently utilizes the functional bus under a power constraint is described. The test schedule is composed of a set of test vector delivery sequences in small chunks, denoted as packets. The utilization of small packet sizes minimizes required buffer sizes while optimizing the functional bus utilization. The experimental results show that the methodology is highly effective compared to previous approaches that do not use the functional bus. The strong results of the proposed approach are particularly highlighted when small bus widths are considered, an important consideration in current SOC designs where increasingly larger bus widths pose routing and reliability challenges.
- 社団法人電子情報通信学会の論文
- 2006-05-05
著者
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Computer Design And Test Lab Nara Institute Of Science And Technology
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YONEDA Tomokazu
Graduate School of Information Science, Nara Institute of Science and Technology
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ORAILOGLU Alex
Computer Science and Engineering Department, University of California San Diego
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Hussin Fawnizu
Grad. School of Information Science, Nara Institute of Science and Technology
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Yoneda Tomokazu
Grad. School of Information Science, Nara Institute of Science and Technology
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Fujiwara Hideo
Grad. School of Information Science, Nara Institute of Science and Technology
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Yoneda Tomokazu
Computer Design And Test Lab Nara Institute Of Science And Technology
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Yoneda Tomokazu
Graduate School Of Information Science Nara Institute Of Science And Technology
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Yoneda Tomokazu
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Orailoglu Alex
Computer Science And Engineering Department University Of California San Diego
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Hussin Fawnizu
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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