A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)

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概要

• 論文の詳細を見る

• With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results show that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also show that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.

• 社団法人電子情報通信学会の論文
• 2006-04-01

著者

• YONEDA Tomokazu

  Nara Institute of Science and Technology (NAIST)

• FUJIWARA Hideo

  Nara Institute of Science and Technology (NAIST)

• Yoneda Tomokazu

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• MIYAZAKI Masahide

  Nara Institute of Science and Technology

• Fujiwara Hideo

  Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn

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