Yoneda Tomokazu | Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

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著作論文

D-10-18 An Approach to Temperature Control During VLSI Test
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
Scheduling Power-Constrained Tests through the SoC Functional Bus
NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (信号処理)
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
Design and Optimization of Transparency-Based TAM for SoC Test
On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
Delay Testing: Improving Test Quality and Avoiding Over-testing
On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing

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