Inoue Michiko | Nara Institute Of Science And Technology:japan Science And Technology Agency Crest

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著作論文

D-10-18 An Approach to Temperature Control During VLSI Test
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
Program-Based Delay Fault Self-Testing of Processor Cores
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)
A Low Power Deterministic Test Using Scan Chain Disable Technique

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