Fujiwara Hideo | Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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概要
関連著者
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Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
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Inoue Michiko
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Inoue Michiko
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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Fujiwara Hideo
Computer Design And Test Lab Nara Institute Of Science And Technology
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Fujiwara Hideo
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Fujiwara Hideo
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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SALUJA Kewal
University of Wisconsin-Madison
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Ohtake Satoshi
Nara Institute Of Science And Technology (naist)
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Ohtake Satoshi
Nara Institute of Science and Technology
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YONEDA Tomokazu
Nara Institute of Science and Technology (NAIST)
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Fujiwara H
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Singh Virendra
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Inoue Michiko
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Ohtake Satoshi
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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SALUJA Kewal
The author is with the University of Wisconsin-Madison
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Singh Virendra
Nara Institute of Science & Technology
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Yoneda Tomokazu
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Saluja K
Department Of Electrical And Computer Engineering University Of Wisconsin-madison
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Gizdarski Emil
Department Of Computer Systems University Of Rousse
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Fujiwara Hideo
Nara Institute Of Science And Technology
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Gizdarski Emil
Department of Computer Systems, University of Rousse
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NAKAMURA Yoshiyuki
Nara Institute of Science and Technology (NAIST)
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Fujiwara Hideo
University of Wisconsin - Madison, U.S.A
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INOUE Tomoo
Hiroshima City University
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NAKAZATO Masato
Nara Institute of Science and Technology (NAIST)
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YOSHIKAWA YUKI
Nara Institute of Science and Technology
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Clouqueur Thomas
Nara Institute Of Science And Technology
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Savir Jacob
New Jersey Institute Of Technology (njit)
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Nakamura Yoshiyuki
Nara Institute Of Science And Technology (naist):nec Electronics Corporation
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SHUTO Akiko
Hiroshima City University
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ICHIHARA Hideyuki
Hiroshima City University
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Imai Masaharu
Osaka University
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Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
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Fujiwara H
Nara Inst. Sci. And Technol. Nara Jpn
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Ooi Chia
Universiti Teknologi Malaysia
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Ooi Chia
Nara Institute Of Science And Technology
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Shirakawa Isao
Osaka University
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Yasuura Hiroto
Department Of Computer Science And Communication Engineering Kyushu University
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Yasuura Hiroto
Department Of Computer Science And Communication Engineering Graduate School Of Information Science
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Inoue T
Hiroshima City Univ. Hiroshima‐shi Jpn
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Fujiwara Hideo
Naist
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CLOUQUEUR Thomas
AMD Corporation
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Yoneda Tomokazu
Nara Institute Of Science And Technology
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Masuda Kimihiko
Nara Institute Of Science And Technology (naist)
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Clouqueur Thomas
Nara Institute Of Science And Technology (naist)
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Yonezawa Tomonori
Matsushita Electric Industrial Co. Ltd.
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Yoshikawa Yuki
Graduate School Of Information Science Nara Institute Of Science And Technology
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Inoue Tomoo
Nara Institute Of Science And Technology
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Fujiwara Hideo
Nara Institute Of Science And Technology Ikoma Nara
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Akino Toshiro
Matsushita
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Gajski Daniel
University of California
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Sasao Tsutom
Kyushu Institute of Technology
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Sato Masao
Waseda University
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Saucier Gabriele
Institut National Polytechnique de Grenoble
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Yonezawa Yomonori
Matsushita Electric Industrial Co., Ltd.
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MIYAZAKI Masahide
Nara Institute of Science and Technology
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Inoue Tomoo
Hiroshima City Univ. Hiroshima‐shi Jpn
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Wakabayashi Shin'ichi
Hiroshima Univ.
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Fujiwara Hideo
Nara Institute Of Technology
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Yasuura Hiroto
Department Of Computer Science And Communication Engineering Graduate School Of Information Science
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Yonezawa Yomonori
Matsushita Electric Industrial Co. Ltd.
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Inoue Michiko
Nara Institute of Science and Technology
著作論文
- Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
- D-10-18 An Approach to Temperature Control During VLSI Test
- Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
- Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
- Program-Based Delay Fault Self-Testing of Processor Cores
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
- Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch(Dependable Computing)
- A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
- Effect of BIST Pretest on IC Defect Level(Dependable Computing)
- Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)
- Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
- A New Class of Sequential Circuits with Acyclic Test Generation Complexity(メモリテイストとテスト生成複雑度,VLSI設計とテスト及び一般)
- Design and Optimization of Transparency-Based TAM for SoC Test
- Fault set partition for efficient width compression
- Non-scan Design for Single-Port-Change Delay Fault Testability