Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)

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概要

• 論文の詳細を見る

• Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.

• 社団法人電子情報通信学会の論文
• 2005-06-01

著者

• FUJIWARA Hideo

  Nara Institute of Science and Technology (NAIST)

• Fujiwara Hideo

  Computer Design And Test Lab Nara Institute Of Science And Technology

• Savir Jacob

  New Jersey Institute Of Technology (njit)

• Fujiwara Hideo

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• NAKAMURA Yoshiyuki

  Nara Institute of Science and Technology (NAIST)

• Fujiwara Hideo

  Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn

• Nakamura Yoshiyuki

  Nara Institute Of Science And Technology (naist):nec Electronics Corporation

関連論文

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• Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
• Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
• Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
• Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
• NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
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• Scheduling Power-Constrained Tests through the SoC Functional Bus
• NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
• Power-Conscious Microprocessor-Based Testing of System-on-Chip
• Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
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• SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
• Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
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• Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
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• Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
• A New Class of Sequential Circuits with Acyclic Test Generation Complexity(メモリテイストとテスト生成複雑度,VLSI設計とテスト及び一般)
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• Fault set partition for efficient width compression
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