Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
スポンサーリンク
概要
- 論文の詳細を見る
While design-for-testability (DFT) techniques are generally used in order to reduce test generation complexity, it induces over-testing problems. In general, DFT techniques make a large number of untestable path delay faults (PDFs) testable. However the PDFs which became testable do not affect the circuit performance even if they exist on paths because they were originally untestable. Therefore we consider that testing such PDFs is over-testing. In this work, we reduce the over-testing by identifying false paths using register transfer level information. Our method identifies a subset of false paths and multi-cycle paths within a reasonable time. Experimental results for some RTL benchmark circuits show that the effectiveness of our false path identification method.
- 社団法人電子情報通信学会の論文
- 2007-02-02
著者
-
Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
-
OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
-
Ohtake Satoshi
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
-
Ohtake Satoshi
Nara Institute Of Science And Technology (naist)
-
Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
-
Fujiwara Hideo
Computer Design And Test Lab Nara Institute Of Science And Technology
-
Fujiwara Hideo
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
-
YOSHIKAWA Yuki
Graduate School of Information Science, Nara Institute of Science and Technology
-
Yoshikawa Yuki
Graduate School Of Information Science Nara Institute Of Science And Technology
-
Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
-
Fujiwara Hideo
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
-
Yoshikawa Yuki
Graduate School Of Information Science Hiroshima City University
関連論文
- Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
- F-Scan: A DFT Method for Functional Scan at RTL
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- On the Effect of Scheduling in Test Generation
- Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
- D-10-18 An Approach to Temperature Control During VLSI Test
- Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
- Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
- Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
- Design for Two-Pattern Testability of Controller-Data Path Circuits
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
- NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
- On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
- Scheduling Power-Constrained Tests through the SoC Functional Bus
- NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
- Power-Conscious Microprocessor-Based Testing of System-on-Chip
- Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation
- A Design Scheme for Delay Testing of Controllers Using State Transition Information
- A Simple Parallel Algorithm for the Medial Axis Transform (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing)
- Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
- Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
- Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
- Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
- Power constrained IP core wrapper design with partitioned clock domains (信号処理)
- Binding Study of Semotiadil and Levosemotiadil with Human Serum Albumin Using High-Performance Frontal Analysis
- Performance Analysis of Parallel Test Generation for Combinational Circuits
- A New Class of Sequential Circuits with Combinational Test Generation Complexity for Path Delay Faults
- Preemptive System-on-Chip Test Scheduling(SoC Testing)(Test and Verification of VLSI)
- Design for Hierarchical Two-Pattern Testability of Data Paths
- A Self-Stabilizing Spanning Tree Protocol that Tolerates Non-quiescent Permanent Faults
- A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability
- Effect of BIST Pretest on IC Defect Level(Dependable Computing)
- Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)
- A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
- Classification of Sequential Circuits Based on Combinational Test Generation Complexity
- A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
- Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)
- F-Scan : A DFT Method for Functional Scan at RTL
- A Low Power Deterministic Test Using Scan Chain Disable Technique
- A secure scan design approach using extended de Bruijn graph (ディペンダブルコンピューティング)
- A New Data Structure for SAT-Based Static Learning With Impact on Test Generation (特集 新アーキテクチャLSI技術および一般)
- Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
- Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
- A-3-9 Analysis of Fault Coverage under a Power Budget in Scan Testing
- A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
- Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
- Hybrid Test Application in Partial Skewed-Load Scan Design
- Non-scan Design for Single-Port-Change Delay Fault Testability
- Methodology for in Situ Protection of Aldehydes and Ketones Using Trimethylsilyl Trifluoromethanesulfonate and Phosphines: Selective Alkylation and Reduction of Ketones, Esters, Amides, and Nitriles