Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
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概要
- 論文の詳細を見る
In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.
- 社団法人電子情報通信学会の論文
- 2007-01-01
著者
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FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
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Ohtake Satoshi
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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Ohtake Satoshi
Nara Institute Of Science And Technology (naist)
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Fujiwara Hideo
Computer Design And Test Lab Nara Institute Of Science And Technology
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Fujiwara Hideo
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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NAKAZATO Masato
Nara Institute of Science and Technology (NAIST)
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SALUJA Kewal
University of Wisconsin-Madison
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Fujiwara Hideo
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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Ohtake Satoshi
Nara Institute of Science and Technology
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