Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch(Dependable Computing)
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概要
- 論文の詳細を見る
In this paper, we provide a practical formulation of the problem of identifying all error occurrences and all failed scan cells in atspeed scan based BIST environment. We propose a method that can be used to identify every error when the circuit test frequency is higher than the tester frequency. Our approach requires very little extra hardware for diagnosis and the test application time required to identify errors is a linear function of the frequency ratio between the CUT and the tester.
- 社団法人電子情報通信学会の論文
- 2006-03-01
著者
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FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
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SALUJA Kewal
University of Wisconsin-Madison
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Clouqueur Thomas
Nara Institute Of Science And Technology (naist)
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Clouqueur Thomas
Nara Institute Of Science And Technology
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NAKAMURA Yoshiyuki
Nara Institute of Science and Technology (NAIST)
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Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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