Effect of BIST Pretest on IC Defect Level(Dependable Computing)

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概要

• 論文の詳細を見る

• In the impact of BIST on the chip defect level after test has been addressed. It was assumed in that no measures are taken to ensure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to get rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when it may be worthwhile to perform it.

• 社団法人電子情報通信学会の論文
• 2006-10-01

著者

• FUJIWARA Hideo

  Nara Institute of Science and Technology (NAIST)

• Fujiwara Hideo

  Computer Design And Test Lab Nara Institute Of Science And Technology

• Fujiwara Hideo

  Nara Institute Of Science And Technology:japan Science And Technology Agency Crest

• Savir Jacob

  New Jersey Institute Of Technology (njit)

• Fujiwara Hideo

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• NAKAMURA Yoshiyuki

  Nara Institute of Science and Technology (NAIST)

• Fujiwara Hideo

  Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn

• Nakamura Yoshiyuki

  Nara Institute Of Science And Technology (naist):nec Electronics Corporation

関連論文

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• SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
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• Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
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