Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
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概要
- 論文の詳細を見る
Rapid developments in VLSI technology has made it possible to embed whole system components onto a single chip, called System-on-Chip or SoC. Recently, SoCs operating at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. Thus, the testing of SoCs and multi-clock domain embedded cores under power constraints is of great importance. This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints.
- 社団法人電子情報通信学会の論文
- 2007-06-15
著者
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Computer Design And Test Lab Nara Institute Of Science And Technology
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Fujiwara Hideo
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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YONEDA Tomokazu
Graduate School of Information Science, Nara Institute of Science and Technology
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Yoneda Tomokazu
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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YU Thomas
Graduate School of Information Science, Nara Institute of Science and Technology
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YU Thomas
Computer Design and Test Lab, Nara Institute of Science and Technology
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ZHAO Danella
The Center For Advanced Computer Studies, University of Louisiana at Lafayette
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Yu Thomas
Computer Design And Test Lab Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Yoneda Tomokazu
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Zhao Danella
The Center For Advanced Computer Studies University Of Louisiana At Lafayette
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Fujiwara Hideo
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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