Delay Testing: Improving Test Quality and Avoiding Over-testing
スポンサーリンク
概要
- 論文の詳細を見る
Delay testing is one of key processes in production test to ensure high quality and high reliability for logic circuits. Test escape missing defective chips can be reduced by introducing delay testing. On the other hand, we need to concern yield loss caused by delay testing, i.e., over-testing. Many methods and techniques have been developed to solve problems on delay testing. In this paper, we introduce fundamental techniques of delay testing and survey recent problems and solutions. Especially we focus on techniques to enhance test quality, to avoid over-testing, and to make test design efficient by treating circuits described at register transfer level.
- Information and Media Technologies 編集運営会議の論文
著者
-
Yoneda Tomokazu
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
-
Kajihara Seiji
Kyushu Inst. Technol. Iizuka‐shi Jpn
-
Ohtake Satoshi
Nara Institute of Science and Technology
関連論文
- Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan(Special Issue on Test and Verification of VLSI)
- D-10-18 An Approach to Temperature Control During VLSI Test
- Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
- Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
- NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
- On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
- Scheduling Power-Constrained Tests through the SoC Functional Bus
- NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
- Power-Conscious Microprocessor-Based Testing of System-on-Chip
- Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
- Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
- Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
- Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
- Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
- Power constrained IP core wrapper design with partitioned clock domains (信号処理)
- High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme
- A Study of Capture-Safe Test Generation Flow for At-Speed Testing
- Scan Tree Design: Test Compression with Test Vector Modification (特集:システムLSIの設計技術と設計自動化)
- A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
- Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
- Design and Optimization of Transparency-Based TAM for SoC Test
- On Delay Test Quality for Test Cubes
- A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
- Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
- A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
- A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
- Non-scan Design for Single-Port-Change Delay Fault Testability
- Estimation of Delay Test Quality and Its Application to Test Generation
- Delay Testing: Improving Test Quality and Avoiding Over-testing
- On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing