Preemptive System-on-Chip Test Scheduling(SoC Testing)(<Special Section>Test and Verification of VLSI)
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概要
- 論文の詳細を見る
In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.
- 社団法人電子情報通信学会の論文
- 2004-03-01
著者
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Fujiwara Hideo
Computer Design And Test Lab Nara Institute Of Science And Technology
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Fujiwara Hideo
Computer Design And Test Laboratory Nara Institute Of Science And Technology
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LARSSON Erik
Embedded Systems Laboratory, Linkopings Universitet
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Larsson Erik
Embedded Systems Laboratory Linkopings Universitet:computer Design And Test Laboratory Nara Institut
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