Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)

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概要

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• Higher power densities and the non-linear spatial distribution of heat of VLSI chips put greater emphasis on chip-packaging and temperature control during test. For system-on-chips, power-based scheduling algorithms are used to optimize tests while satisfying power budgets. However, it has been shown that power-constrained test scheduling does not ensure thermal safety due to the non-uniform power distribution across the chip. In this paper, we present a test schedule optimization method for system-on-chips using cycle-accurate power profiles for thermal simulation, test partitioning, and interleaving that ensures thermal safety while still optimizing the test schedule. Our method uses a simplified thermal-cost model and bin-packing algorithm to ensure that the maximum temperatures of SoCs with fixed TAM and core assignments satisfy the temperature constraints with minimum increases in test application time.

• 社団法人電子情報通信学会の論文
• 2007-11-14

著者

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Chakrabarty Krishnendu

  Electrical And Computer Engineering Duke University

• Fujiwara Hideo

  Computer Design And Test Lab Nara Institute Of Science And Technology

• Fujiwara Hideo

  Nara Institute Of Science And Technology:japan Science And Technology Agency Crest

• YONEDA Tomokazu

  Graduate School of Information Science, Nara Institute of Science and Technology

• Yoneda Tomokazu

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• YU Thomas

  Graduate School of Information Science, Nara Institute of Science and Technology

• YU Thomas

  Computer Design and Test Lab, Nara Institute of Science and Technology

• Yu Thomas

  Computer Design And Test Lab Nara Institute Of Science And Technology

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Yoneda Tomokazu

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• Fujiwara Hideo

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

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