Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
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概要
- 論文の詳細を見る
This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.
- （社）電子情報通信学会の論文
- 2008-03-01
著者
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YONEDA Tomokazu
Nara Institute of Science and Technology (NAIST)
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FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
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Masuda Kimihiko
Nara Institute Of Science And Technology (naist)
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Yoneda Tomokazu
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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