A New Class of Sequential Circuits with Acyclic Test Generation Complexity(メモリテイストとテスト生成複雑度,VLSI設計とテスト及び一般)
スポンサーリンク
概要
- 論文の詳細を見る
This paper introduces a new class of sequential circuits called acyclically testable sequential circuits, whose test generation complexity is equivalent to that of the acyclic sequential circuits. A procedure to perform test generation on acyclically testable sequential circuits is elaborated and a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuits is also presented. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
- 社団法人電子情報通信学会の論文
- 2006-02-10
著者
-
Ooi Chia
Nara Institute Of Science And Technology
-
Clouqueur Thomas
Nara Institute Of Science And Technology
-
Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
関連論文
- Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
- D-10-18 An Approach to Temperature Control During VLSI Test
- Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
- Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
- Program-Based Delay Fault Self-Testing of Processor Cores
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
- Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch(Dependable Computing)
- A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
- Effect of BIST Pretest on IC Defect Level(Dependable Computing)
- Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)
- Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
- A New Class of Sequential Circuits with Acyclic Test Generation Complexity(メモリテイストとテスト生成複雑度,VLSI設計とテスト及び一般)
- Design and Optimization of Transparency-Based TAM for SoC Test
- Fault set partition for efficient width compression
- Non-scan Design for Single-Port-Change Delay Fault Testability