Program-Based Delay Fault Self-Testing of Processor Cores
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概要
- 論文の詳細を見る
This paper proposes an efficient methodology of delay fault testing of processor cores using its instruction set. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible. A delay fault will affect the functionality only when it can be activated in functional mode. There are some paths, which are never excited in the functional mode of operation ; hence these are functionally untestable paths. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a funite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraciton of constraints for the paths that can potentially be tested. Path delay fault model is used. The experimental results on Parwan processor demonstrate the effectiveness of our method.
- 一般社団法人情報処理学会の論文
- 2003-11-27
著者
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FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
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Fujiwara H
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Singh Virendra
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Inoue Michiko
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Inoue Michiko
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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SALUJA Kewal
University of Wisconsin-Madison
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SALUJA Kewal
The author is with the University of Wisconsin-Madison
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Singh Virendra
Nara Institute of Science & Technology
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Inoue Michiko
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Saluja K
Department Of Electrical And Computer Engineering University Of Wisconsin-madison
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Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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