Transistor Leakage Fault Diagnosis for CMOS Circuits(Special Issue on Test and Diagnosis of VLSI)
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概要
- 論文の詳細を見る
This paper presents a new methodology for diagnosing transistor leakage faults in a CMOS circuit by using both I_<DDQ> and logic value information. A hierarchical procedure is used to identify and delete impossible fault candidates efficiently and a procedure is employed to generate diagnostic tests for improving diagnostic resolution. A novel approach for handling the intermediate output voltage of a faulty gate is used in new methods for fault simulation and diagnostic test generation based on primary output values. Experimental results on ISCAS'85 circuits show the effectiveness of the proposed methodology.
- 社団法人電子情報通信学会の論文
- 1998-07-25
著者
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WEN Xiaoqing
Kyushu Institute of Technology
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Kawano K
Okayama Univ. Okayama‐shi Jpn
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Tamamoto H
The Department Of Information Engineering Akita University
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Tamamoto Hideo
The Department Of Information Engineering Akita University
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Kawano K
Information Technology Center Okayama University
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Saluja K
Department Of Electrical And Computer Engineering University Of Wisconsin-madison
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Saluja Kewal
Department Of Electrical And Computer Engineering University Of Wisconsin-madison
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Saluja Kewal
Univ. Wisconsin‐madison Usa
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Wen Xiaoqing
Faculty Of Computer Science And Systems Engineering Kyushu Institute Of Technology
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Kinoshita K
Department Of Information Networking Graduate School Of Information Science And Technology Osaka Uni
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Kinoshita Kozo
Faculty Of Informatics Osaka Gakuin University
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Xiaoqing WEN
the Department of Information Engineering, Akita University
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SALUJA Kewal
the Department of Electrical and Computer Engineering, University of Wisconsin
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KINOSHITA Kozo
the Department of Applied Physics, Osaka University
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Xiaoqing Wen
Department Of Information Engineering Mining College Akita University
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Xiaoqing Wen
The Department Of Information Engineering Akita University
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Saluja Kewal
The Department Of Electrical And Computer Engineering University Of Wisconsin
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