Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
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概要
- 論文の詳細を見る
This paper deals with delay faults on clock lines assuming the launch-on-capture test. In this realistic fault model, the amount of delay at the FF driven by the faulty clock line is such that the scan shift operation can perform correctly even in the presence of a fault, but during the system clock operation, capturing functional value(s) at faulty FF(s), i.e. FF(s) driven by the clock with delay, is delayed and correct value(s) may not be captured. We developed a fault simulator that can handle such faults and using this simulator we investigate the relation between the duration of the delay and the difficulty of detecting clock delay faults in the launch-on-capture test. Next, we propose test generation methods for detecting clock delay faults that affect a single or two FFs. Experimental results for benchmark circuits are given in order to establish the effectiveness of the proposed methods.
著者
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HIGAMI Yoshinobu
Graduate School of Science and Engineering, Ehime University
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KOBAYASHI Shin-ya
Graduate School of Science and Engineering, Ehime University
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SALUJA Kewal
University of Wisconsin-Madison
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Takahashi Hiroshi
Graduate School Of Environmental Studies Tohoku University
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