SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, we present an efficient and robust test generation algorithm for combinational circuits based on the Boolean satisfiability method called SPIRIT.We elaborate some well-known techniques as well as present some new techniques that improve performance and robustness of test generation algorithms.As a result, SPIRIT achieves 100% fault efficiency for full scan version of the ITC'99 benchmark circuits in a reasonable amount of time.
- 社団法人電子情報通信学会の論文
- 2000-11-23
著者
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FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
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Fujiwara Hideo
Nara Institute Of Science And Technology
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Gizdarski Emil
Department of Computer Systems, University of Rousse
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Gizdarski Emil
Department Of Computer Systems University Of Rousse
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Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
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- SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
- Performance Analysis of Parallel Test Generation for Combinational Circuits
- Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
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- Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
- A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
- A New Class of Sequential Circuits with Acyclic Test Generation Complexity(メモリテイストとテスト生成複雑度,VLSI設計とテスト及び一般)
- Design and Optimization of Transparency-Based TAM for SoC Test
- A New Data Structure for SAT-Based Static Learning With Impact on Test Generation (特集 新アーキテクチャLSI技術および一般)
- Fault set partition for efficient width compression
- Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
- Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
- Non-scan Design for Single-Port-Change Delay Fault Testability