A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)

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概要

• 論文の詳細を見る

• This paper presents a non-scan design-far-testability (DFT) method for VLSIs designed at register-transfer level (RTL) to achieve complete fault efficiency. In KTL design, a VLSI generally consists of a controller and a data path. The proposed method mainly consists of the following two steps. First, DFT methods are applied to the controller and the data path, separately. Then, a test plan generator is appended to support at-speed testing. The test plan generator generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can significantly reduce both the test generation time and the test application time in comparison with full-scan design, though the hardware overhead of our method is slightly larger than that of full-scan design.

• 一般社団法人情報処理学会の論文
• 2003-05-15

著者

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Fujiwara Hideo

  The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno

• OHTAKE Satoshi

  Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)

• Ohtake S

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Ohtake Satoshi

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Fujiwara Hideo

  Naist

• Fujiwara Hideo

  Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Nara Institute Of Science And Technology

• MASUZAWA Toshimitsu

  the Graduate School of Information Science and Technology, Osaka University

• Masuzawa Toshimitsu

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Masuzawa Toshimitsu

  Nara Institute Of Sciences And Technology

• Masuzawa Toshimitsu

  Department Of Informatics And Mathematical Science Graduate School Of Engineering Science

• Masuzawa Toshimitsu

  Department Of Computer Science Graduate School Of Information Science And Technology Osaka Universit

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Wada Hiroki

  Central Research Laboratory Hitachi Ltd.

• Fujiwara H

  Nara Inst. Sci. And Technol. Kansai Science City Jpn

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