A-3-9 Analysis of Fault Coverage under a Power Budget in Scan Testing
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概要
- 論文の詳細を見る
- 社団法人電子情報通信学会の論文
- 2007-08-29
著者
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
関連論文
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
- Design for Two-Pattern Testability of Controller-Data Path Circuits
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
- New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation
- A Design Scheme for Delay Testing of Controllers Using State Transition Information
- A New Class of Sequential Circuits with Combinational Test Generation Complexity for Path Delay Faults
- Design for Hierarchical Two-Pattern Testability of Data Paths
- An integer programming formulation for generating high quality transition tests (システムLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (ディペンダブルコンピューティング・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (VLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- A-3-5 A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs
- A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
- F-Scan : A DFT Method for Functional Scan at RTL
- A-3-9 Analysis of Fault Coverage under a Power Budget in Scan Testing
- A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
- Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
- Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer