A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
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概要
- 論文の詳細を見る
This paper discusses a test generation framework using checker circuits. In this framework, some properties, which should be considered during test generation, are expressed as a checker circuit, then; for the circuit under test attached to the checker circuit and its mask circuit, test generation is performed by using existing techniques. Any test set generated under the framework satisfies all the properties given by the user. This framework can handle various properties together by using checker circuits, and it can easily be implemented. In this paper, as a possible application of the framework, path delay test generation through stuck-at test generation is presented. Experimental results show that the proposed framework is feasible and effective.
- 社団法人電子情報通信学会の論文
- 2007-01-23
著者
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KANEKO Mineo
School of Information Science, Japan Advanced Institute of Science and Technology
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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Fujiwara H
Nara Inst. Of Sci. And Technol. Nara Jpn
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Kaneko Mineo
Japan Advanced Inst. Of Sci. And Technol. Ishikawa Jpn
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Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
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