Iwagaki Tsuyoshi | School Of Information Science Japan Advanced Institute Of Science And Technology
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概要
関連著者
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology
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KANEKO Mineo
School of Information Science, Japan Advanced Institute of Science and Technology
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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Fujiwara H
Nara Inst. Of Sci. And Technol. Nara Jpn
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Kaneko Mineo
Japan Advanced Inst. Of Sci. And Technol. Ishikawa Jpn
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INOUE Keisuke
School of Information Science, Japan Advanced Institute of Science and Technology
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Inoue Keisuke
School Of Information Science Japan Advanced Institute Of Science And Technology
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
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Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
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TAKEDA Eiri
School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
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Takeda Eiri
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
著作論文
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- An integer programming formulation for generating high quality transition tests (システムLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (ディペンダブルコンピューティング・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (VLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- A-3-5 A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs
- A-3-9 Analysis of Fault Coverage under a Power Budget in Scan Testing
- Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
- Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer