Kaneko Mineo | School Of Information Science Japan Advanced Institute Of Science And Technology
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概要
- KANEKO Mineoの詳細を見る
- 同名の論文著者
- School Of Information Science Japan Advanced Institute Of Science And Technologyの論文著者
関連著者
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Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology
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KANEKO Mineo
School of Information Science, Japan Advanced Institute of Science and Technology
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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INOUE Keisuke
School of Information Science, Japan Advanced Institute of Science and Technology
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Kaneko Mineo
Japan Advanced Inst. Of Sci. And Technol. Ishikawa Jpn
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Inoue Keisuke
School Of Information Science Japan Advanced Institute Of Science And Technology
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Kaneko M
Japan Advanced Inst. Sci. And Technol. Jpn
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Tokuda K
Department Of Computer Science And Engineering Nagoya Institute Of Technology
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Tokuda Keiichi
Department Of Computer Science And Engineering Nagoya Institute Of Technology
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Tokuda Keiichi
The Department Of Computer Science Nagoya Institute Of Technology
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TOKUDA Keiichi
Department of Computer Science and Engineering, Nagoya Institute of Technology
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Resende F
Tokyo Inst. Technol. Tokyo Jpn
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NISHIHARA Akinori
Department of Physical Electronics, Faculty of Engineering, Tokyo Institute of Technology
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Inoue Keisuke
Department of Anatomy & Neurobiology, Kyoto Prefectural University of Medicine
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Nishihara A
Tokyo Inst. Technol. Tokyo Jpn
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Ohashi Koji
School Of Information Science Japan Advanced Institute Of Science And Technology
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Nishihara Akinori
Department Communications And Integrated Systems Tokyo Institute Of Technology
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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Fujiwara H
Nara Inst. Of Sci. And Technol. Nara Jpn
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Kaneko M
Japan Advanced Inst. Sci. And Technol. Ishikawa‐ken Jpn
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Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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Obata Takayuki
School Of Information Science At Japan Advanced Institute Of Science And Technology
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Tokuda Keiichi
Ee
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RESENDE Fernando
Department of Electronics and Computer Science
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Obata Takayuki
School Of Information Science Japan Advanced Institute Of Science And Technology
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Kaneko Mineo
Federal University Of Rio De Janeiro
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Ohashi K
School Of Information Science Japan Advanced Institute Of Science And Technology
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MIYAUCHI Hiroyuki
Department of Chemical Engineering, Graduate School of Engineering, Tohoku University
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DINIZ Paulo
Prog. de Engenharia Eletrica e Depto. de Eletronica, COPPE
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RESENDE Jr.
Department of Physical Electronics, Tokyo Institute of Technology
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Diniz Paulo
Prog. De Engenharia Eletrica E Depto. De Eletronica Coppe
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RESENDE Fernando
Faculty of Engineering, Tokyo Institute of Technology
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YOROZUYA Toshiyuki
School of Information Science, Japan Advanced Institute of Science and Technology
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TAYU Satoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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Nishihara Akinori
Center For Research And Development Of Educational Technology Tokyo Institute Of Technology
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Resende Jr.
Department Of Physical Electronics Tokyo Institute Of Technology
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Yorozuya Toshiyuki
School Of Information Science Japan Advanced Institute Of Science And Technology
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Tayu Satoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
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Miyauchi Hiroyuki
Department Of Chemical Engineering Graduate School Of Engineering Tohoku University
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TAKEDA Eiri
School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
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Takeda Eiri
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
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INOUE Keisuke
Department of Global Information Technology, Kanazawa Technical College
著作論文
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
- LMS-Based Algorithms with Multi-Band Decomposition of the Estimation Error Applied to System Identification (Special Section on Digital Signal Processing)
- Multi-Band Decomposition of the Linear Prediction Error Applied to Adaptive AR Spectral Estimation
- Adaptive AR Spectral Estimation Based on Wavelet Decomposition of the Linear Prediction Error
- An integer programming formulation for generating high quality transition tests (システムLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis
- An integer programming formulation for generating high quality transition tests (ディペンダブルコンピューティング・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (VLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
- Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems
- A-3-5 A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs
- Characterization and Computation of Steiner Routing Based on Elmore's Delay Model
- Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
- Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
- A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths
- Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle
- Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation