Fujiwara Hideo | Graduate School Of Information Of Science Nara Institute Of Science And Technology

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
On the Effect of Scheduling in Test Generation
Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
Design for Two-Pattern Testability of Controller-Data Path Circuits
Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
Scheduling Power-Constrained Tests through the SoC Functional Bus
NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation
A Design Scheme for Delay Testing of Controllers Using State Transition Information
A Simple Parallel Algorithm for the Medial Axis Transform (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing)
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (信号処理)
Performance Analysis of Parallel Test Generation for Combinational Circuits
A New Class of Sequential Circuits with Combinational Test Generation Complexity for Path Delay Faults
Design for Hierarchical Two-Pattern Testability of Data Paths
A Self-Stabilizing Spanning Tree Protocol that Tolerates Non-quiescent Permanent Faults
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
Classification of Sequential Circuits Based on Combinational Test Generation Complexity
A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)
F-Scan : A DFT Method for Functional Scan at RTL
A Low Power Deterministic Test Using Scan Chain Disable Technique
A secure scan design approach using extended de Bruijn graph (ディペンダブルコンピューティング)
A New Data Structure for SAT-Based Static Learning With Impact on Test Generation (特集新アーキテクチャLSI技術および一般)
Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design

もっと見る

スポンサーリンク