Design for Two-Pattern Testability of Controller-Data Path Circuits

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概要

• 論文の詳細を見る

• This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.

• 社団法人電子情報通信学会の論文
• 2003-06-01

著者

• ALTAF-UL-AMIN Md.

  Graduate School of Information Science, Nara Institute of Science and Technology

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Fujiwara Hideo

  The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno

• OHTAKE Satoshi

  Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)

• Ohtake S

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Ohtake Satoshi

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Altaf-ul-amin Md.

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Altaf‐ul‐amin M

  Graduate School Of Information Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Naist

• Fujiwara Hideo

  Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Nara Institute Of Science And Technology

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Fujiwara H

  Nara Inst. Sci. And Technol. Kansai Science City Jpn

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