A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

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概要

• 論文の詳細を見る

• Since scan testing is not based on the function of the circuit, but rather the structure, it is considered to be both a form of over testing and under testing. Moreover, it is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a fault-dependent test generation method to detect specified fault models completely and to increase defect coverage as much as possible under the test length constraint. We present experimental results for MCNC91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and to show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.

• （社）電子情報通信学会の論文
• 2010-01-01

著者

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• HOSOKAWA Toshinori

  College of Industrial Technology, Nihon University

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Inoue Ryoichi

  Graduate School Of Industrial Technology Nihon University

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology (naist)

• Hosokawa Toshinori

  College Of Industrial Technology Nihon University

関連論文

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• On the Effect of Scheduling in Test Generation
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• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
• Design for Two-Pattern Testability of Controller-Data Path Circuits
• Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
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• New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
• NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
• On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
• Scheduling Power-Constrained Tests through the SoC Functional Bus
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• Power-Conscious Microprocessor-Based Testing of System-on-Chip
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• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
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• A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
• Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
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