F-Scan: A DFT Method for Functional Scan at RTL
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概要
- 論文の詳細を見る
Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of todays more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.
著者
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OBIEN Marie
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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