Performance Analysis of Parallel Test Generation for Combinational Circuits

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概要

• 論文の詳細を見る

• The problem of test generation for VLSI circuits computationally requires prohibitive costs. Parallel processing on a multiprocessor system is one of available methods in order to speedup the process for such time-consuming problems. In this paper, we analyze the performance of parallel test generation for combinational circuits. We present two types of parallel test generation systems in which the communication methods are different; vector broadcasting (VB) and fault broadcasting (FB) systems, and analyze the number of generated test vectors, the costs of test vector generation, fault simulation and communication, and the speedup of these parallel test generation systems, where the two types of communication factors; the communication cut-off factor and the communication period, are applied. We also present experimental results on the VB and FB systems implemented on a network of workstations using ISCAS'85 and ISCAS'89 benchmark circuits. The analytical and experimental results show that the total number of test vectors generated in the VB system is the same as that in the FB system, the speedup of the FB system is larger than that of the VB, and it is effective in reducing the communication cost to switch broadcasted data from vectors to faults

• 社団法人電子情報通信学会の論文
• 1996-09-25

著者

• INOUE Tomoo

  Hiroshima City University

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Inoue T

  Hiroshima City Univ. Hiroshima‐shi Jpn

• INOUE Tomoo

  Graduate School of Information Science, Nara Institute of Science and Technology

• Fujiwara Hideo

  Naist

• Fujiwara Hideo

  Nara Institute Of Science And Technology

• Inoue Tomoo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• FUJII Takaharu

  Graduate School of Information Science, Nara Institute of Science and Technology

• Fujii Takaharu

  Graduate School Of Information Science Nara Institute Of Science And Technology:lsi Operation Unit N

• Inoue Tomoo

  Graduate School Of Information Science Hiroshima City University

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