A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability
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概要
- 論文の詳細を見る
This paper proposes a new methodology for testing a core-based systems-on-a-chip (SoC) based on a new concept of testability called consecutive testability. A design for testability (DFT) method for the consecutive testability is also proposed. The proposed method can test interconnections between cores thoroughly. Moreover, the method can test not only for logic faults such as stuck-at faults, but also timing faults such as delay faults that require consecutive application of test patterns at speed of system clock.
- 社団法人電子情報通信学会の論文
- 2002-02-01
著者
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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YONEDA Tomokazu
Graduate School of Information Science, Nara Institute of Science and Technology
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Yoneda Tomokazu
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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