Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper we analyze the testability of RTL data paths targeting all detectable path delay faults.The concept of RTL path is introduced.Based on this concept a definition for 2-pattern(path delay fault)testable data path is developed.Some necessary and sufficient conditions to support the propagation of 2-pattern vectors for two or more control paths are pointed out.A graph approach of our analysis is also presented.

• 社団法人電子情報通信学会の論文
• 2000-11-23

著者

• ALTAF-UL-AMIN Md.

  Graduate School of Information Science, Nara Institute of Science and Technology

• Fujiwara Hideo

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Fujiwara Hideo

  The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno

• OHTAKE Satoshi

  Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)

• Ohtake S

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Ohtake Satoshi

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Altaf-ul-amin Md.

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Altaf‐ul‐amin M

  Graduate School Of Information Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Naist

• Fujiwara Hideo

  Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Nara Institute Of Science And Technology

• Fujiwara Hideo

  Graduate School Of Information Of Science Nara Institute Of Science And Technology

• Fujiwara H

  Nara Inst. Sci. And Technol. Kansai Science City Jpn

関連論文

• Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
• Metabolic pathway prediction based on inclusive relation between cyclic substructures
• Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector
• MetalMine : a database of functional metal-binding sites in proteins
• KNApSAcK gene classification system for Arabidopsis thaliana : Comparative genomic analysis of unicellular to seed plants
• Predicting conformation of protein complexes by determining statistically significant domain-domain interactions
• DrEFTIR : The data mining software for fourier transform near-infrared reflectance spectroscopy focused on food metabolic finger printing
• An approach to peak detection in GC-MS chromatograms and application of KNApSAcK database in prediction of candidate metabolites
• F-Scan: A DFT Method for Functional Scan at RTL
• Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• On the Effect of Scheduling in Test Generation
• Testing for the Programming Circuit of SRAM-Based FPGAs
• Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
• Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
• A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
• Design for Two-Pattern Testability of Controller-Data Path Circuits
• Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
• Elucidating Conservation of Genes in Multiple Genomes Based on Graphs Configured by Bidirectional Best-Hit Relationships
• NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
• On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
• Scheduling Power-Constrained Tests through the SoC Functional Bus
• NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
• Power-Conscious Microprocessor-Based Testing of System-on-Chip
• Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
• Comparison of Protein Complexes Predicted from PPI Networks by DPClus and Newman Clustering Algorithms
• Spherical SOM and Arrangement of Neurons Using Helix on Sphere (特集:第11回MPSシンポジウム--複雑系の科学とその応用)
• Delay Fault Testing of Processor Cores in Functional Mode(Dependable Computing)
• A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
• A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
• A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
• A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
• A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
• Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation
• A Design Scheme for Delay Testing of Controllers Using State Transition Information
• Wait-Free Linearizable Distributed Shared Memory
• Parallel Algorithms for the All Nearest Neighbors of Binary Image on the BSP Model
• High-Level Synthesis for Weakly Testable Data Paths(Special Issue on Test and Diagnosis of VLSI)
• A Simple Parallel Algorithm for the Medial Axis Transform (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing)
• Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
• Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
• Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
• Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
• Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
• Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
• Power constrained IP core wrapper design with partitioned clock domains (信号処理)
• Performance Analysis of Parallel Test Generation for Combinational Circuits
• Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
• A New Class of Sequential Circuits with Combinational Test Generation Complexity for Path Delay Faults
• SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• Design for Hierarchical Two-Pattern Testability of Data Paths
• A Self-Stabilizing Spanning Tree Protocol that Tolerates Non-quiescent Permanent Faults
• A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability
• A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
• Classification of Sequential Circuits Based on Combinational Test Generation Complexity
• A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
• Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)
• F-Scan : A DFT Method for Functional Scan at RTL
• A Low Power Deterministic Test Using Scan Chain Disable Technique
• A secure scan design approach using extended de Bruijn graph (ディペンダブルコンピューティング)
• A New Data Structure for SAT-Based Static Learning With Impact on Test Generation (特集 新アーキテクチャLSI技術および一般)
• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
• A-3-9 Analysis of Fault Coverage under a Power Budget in Scan Testing
• A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
• Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
• SS-mPMG and SS-GA : Tools for Finding Pathways and Dynamic Simulation of Metabolic Networks
• Systematization of the Protein Sequence Diversity in Enzymes Related to Secondary Metabolic Pathways in Plants, in the Context of Big Data Biology Inspired by the KNApSAcK Motorcycle Database

もっと見る 閉じる

スポンサーリンク