Fujiwara Hideo | Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)

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著作論文

Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector
A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
Design for Two-Pattern Testability of Controller-Data Path Circuits
Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Wait-Free Linearizable Distributed Shared Memory
Parallel Algorithms for the All Nearest Neighbors of Binary Image on the BSP Model
High-Level Synthesis for Weakly Testable Data Paths(Special Issue on Test and Diagnosis of VLSI)
A Simple Parallel Algorithm for the Medial Axis Transform (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing)
A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis

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