Hosokawa T | Starc
スポンサーリンク
概要
関連著者
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Date Hiroshi
Starc
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MURAOKA Michiaki
STARC
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Hosokawa T
Starc
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Muraoka M
Starc (semiconductor Technol. Academic Res. Center) Yokohama‐shi Jpn
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MURAOKA Michiaki
Design Technology Development Department, Semiconductor Technology Academic Research Center (STARC)
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Fujiwara Hideo
The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno
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Fujiwara Hideo
Naist
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Fujiwara Hideo
Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)
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Fujiwara Hideo
Nara Institute Of Science And Technology
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Fujiwara H
Nara Inst. Sci. And Technol. Kansai Science City Jpn
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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HOSOKAWA Toshinori
College of Industrial Technology, Nihon University
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DATE Hiroshi
System JD Co., Ltd.
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MIYAZAKI Masahide
Design Technology Development Department, Semiconductor Technology Academic Research Center (STARC)
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HOSOKAWA TOSHINORI
Design Technology Development Department, Semiconductor Technology Academic Research Center(STARC)
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DATE HIROSHI
Design Technology Development Department, Semiconductor Technology Academic Research Center(STARC)
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Hosokawa Toshinori
College Of Industrial Technology Nihon University
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Miyazaki Masahide
Design Technology Development Department Semiconductor Technology Academic Research Center (starc)
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MIYAZAKI Masahide
STARC
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HOSOKAWA Toshinori
STARC
著作論文
- A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
- A Test State Reduction Method for FSMs with Non-Scan DFT Using Don't Care Inputs Identification Technique (特集:システムLSIの設計技術と設計自動化)
- Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits(Special Issue on Test and Verification of VLSI)