Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits(Special Issue on Test and Verification of VLSI)

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概要

• 論文の詳細を見る

• This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

• 社団法人電子情報通信学会の論文
• 2002-10-01

著者

• Date Hiroshi

  Starc

• MURAOKA Michiaki

  STARC

• MURAOKA Michiaki

  Design Technology Development Department, Semiconductor Technology Academic Research Center (STARC)

• HOSOKAWA TOSHINORI

  Design Technology Development Department, Semiconductor Technology Academic Research Center(STARC)

• DATE HIROSHI

  Design Technology Development Department, Semiconductor Technology Academic Research Center(STARC)

• Hosokawa T

  Starc

• Muraoka M

  Starc (semiconductor Technol. Academic Res. Center) Yokohama‐shi Jpn

関連論文

• A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
• A Test State Reduction Method for FSMs with Non-Scan DFT Using Don't Care Inputs Identification Technique (特集:システムLSIの設計技術と設計自動化)
• Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits(Special Issue on Test and Verification of VLSI)

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