A Test State Reduction Method for FSMs with Non-Scan DFT Using Don't Care Inputs Identification Technique (特集:システムLSIの設計技術と設計自動化)
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概要
- 論文の詳細を見る
This paper proposes a method to reduce the number of states for testing an FSM (Finite State Machine) with non-scan DFT (Design for Testability) using a don't care inputs identification technique. The proposed method reduces the numbers of states required for the FSM testing using a don't care inputs identification technique and a state compaction technique although states required for FSM testing are classified into valid test states and invalid test states. The test length can be shortened by reducing the number of valid test states. Test area for the DFT decreases by reducing the number of invalid test states. Experimental results for MCNC'91 FSM benchmarks and practical FSMs show that, compared with a previous DFT Method, the proposed method reduces the test area by 13 to 77% and shorten the test lengths by 10 to 36%.
- 一般社団法人情報処理学会の論文
- 2003-05-15
著者
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Date Hiroshi
Starc
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MURAOKA Michiaki
STARC
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MURAOKA Michiaki
Design Technology Development Department, Semiconductor Technology Academic Research Center (STARC)
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HOSOKAWA TOSHINORI
Design Technology Development Department, Semiconductor Technology Academic Research Center(STARC)
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DATE HIROSHI
Design Technology Development Department, Semiconductor Technology Academic Research Center(STARC)
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Hosokawa T
Starc
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Muraoka M
Starc (semiconductor Technol. Academic Res. Center) Yokohama‐shi Jpn
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- A Test State Reduction Method for FSMs with Non-Scan DFT Using Don't Care Inputs Identification Technique (特集:システムLSIの設計技術と設計自動化)
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