A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(<Special Section>Test and Verification of VLSI)
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概要
- 論文の詳細を見る
This paper proposes an SoC test architecture generation framework. It contains a database, which stores the test cost information of several DFTs for every core, and a DFT selection part which performs DFT selection for minimizing the test application time using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm that solves this problem is proposed. Experimental results show that bottlenecks in test application time when using a single DFT method for all cores in an SoC is reduced by performing DFT selection from two types of DFTs. As a result, the whole test application time is drastically shortened.
- 社団法人電子情報通信学会の論文
- 2004-03-01
著者
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Fujiwara Hideo
The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno
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Date Hiroshi
Starc
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Fujiwara Hideo
Naist
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Fujiwara Hideo
Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)
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Fujiwara Hideo
Nara Institute Of Science And Technology
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MIYAZAKI Masahide
STARC
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HOSOKAWA Toshinori
STARC
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MURAOKA Michiaki
STARC
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Fujiwara H
Nara Inst. Sci. And Technol. Kansai Science City Jpn
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Hosokawa T
Starc
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Muraoka M
Starc (semiconductor Technol. Academic Res. Center) Yokohama‐shi Jpn
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