High-Level Synthesis for Weakly Testable Data Paths(Special Issue on Test and Diagnosis of VLSI)

スポンサーリンク

概要

• 論文の詳細を見る

• We present a high-level synthesis scheme that considers weak testability of generated register-transfer level(RTL)data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.

• 社団法人電子情報通信学会の論文
• 1998-07-25

著者

• Fujiwara Hideo

  The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno

• Inoue M

  Graduate School Of Information Science Nara Institute Of Science And Technology

• FUJIWARA Hideo

  the Graduate School of Information Science, Nara Institute of Science and Technology

• Fujiwara Hideo

  Naist

• Fujiwara Hideo

  Graduate School Of Infromation Science Nara Institute Of Science And Technology (naist)

• Fujiwara Hideo

  Nara Institute Of Science And Technology

• MASUZAWA Toshimitsu

  the Graduate School of Information Science and Technology, Osaka University

• INOUE Michiko

  the Graduate School of Information Science, Nara Institute of Science and Technology(NAIST)

• NODA Kenji

  ULSI Systems Development Laboratories, NEC Corporation

• HIGASHIMURA Takeshi

  IBM Japan Ltd.

• Masuzawa Toshimitsu

  Graduate School Of Information Science Nara Institute Of Science And Technology

• Masuzawa Toshimitsu

  Nara Institute Of Sciences And Technology

• Masuzawa Toshimitsu

  The Graduate School Of Information Science And Technology Osaka University

• Masuzawa Toshimitsu

  Department Of Computer Science Graduate School Of Information Science And Technology Osaka Universit

• Fujiwara Hideo

  The Graduate School Of Information Science Nara Institute Of Science And Technology

• Fujiwara H

  Nara Inst. Sci. And Technol. Kansai Science City Jpn

• Noda K

  Ulsi Systems Development Laboratories Nec Corporation

• Inoue Michiko

  The Graduate School Of Information Science Nara Institute Of Science And Technology(naist)

• Noda Kenji

  Ulsi Device Development Laboratories Nec Corporation

関連論文

• Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
• Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector
• On the Effect of Scheduling in Test Generation
• Testing for the Programming Circuit of SRAM-Based FPGAs
• Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
• A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
• A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
• Design for Two-Pattern Testability of Controller-Data Path Circuits
• Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• Analyzing Path Delay Fault Testability of RTL Data Paths: A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• Timed Uniform Atomic Broadcast in Presence of Crash and Timing Faults(Foundations of Computer Science)
• Delay Fault Testing of Processor Cores in Functional Mode(Dependable Computing)
• Wait-Free Linearizable Distributed Shared Memory
• Parallel Algorithms for the All Nearest Neighbors of Binary Image on the BSP Model
• High-Level Synthesis for Weakly Testable Data Paths(Special Issue on Test and Diagnosis of VLSI)
• A Simple Parallel Algorithm for the Medial Axis Transform (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing)
• A Parallel Method for the Prefix Convex Hulls Problem
• Distributed Leader Election on Chordal Ring Networks
• Performance Analysis of Parallel Test Generation for Combinational Circuits
• Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
• Homogeneity of Superconductivity in YBa_2Cu_30_x Single Crystals
• Scheduling for Independent-Task Applications on Heterogeneous Parallel Computing Environments under the Unidirectional One-Port Model(Parallel and Distributed Computing,Foundations of Computer Science)
• Scheduling for Gather Operation in Heterogeneous Parallel Computing Environments
• SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
• A Self-Stabilizing Spanning Tree Protocol that Tolerates Non-quiescent Permanent Faults
• Crystal Growth Mechanism of YBa_2Cu_3O_x from Coexisting Region of Solid with Melt
• Fault-Tolerance of Distributed Algorithms : Self-Stabilization and Wait-Freedom(Special Issue on Algorithm Engineering : Surveys)
• A Non-scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency (特集:システムLSIの設計技術と設計自動化)
• Parallel Selection Algorithms for CGM and BSP Models with Application to Sorting (特集 並列処理) -- (並列・分散アルゴリズム)
• Efficient Linearizable Implementation of Shared FIFO Queues and General Objects on a Distributed System(Special Section on Discrete Mathematics and Its Applications)
• Hot-Carrier Reliability of 0.1μm Delta-Doped MOSFETs
• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis(Fault Tolerance)
• Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
• Test Pattern Ordering and Selection for High Quality Test Set under Constraints

もっと見る 閉じる

スポンサーリンク