Delay Fault Testing of Processor Cores in Functional Mode(Dependable Computing)
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概要
- 論文の詳細を見る
This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.
- 社団法人電子情報通信学会の論文
- 2005-03-01
著者
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INOUE Michiko
The authors are with the Graduate School of Information Science, Nara Institute of Science and Techn
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FUJIWARA Hideo
The authors are with the Graduate School of Information Science, Nara Institute of Science and Techn
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Fujiwara H
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Fujiwara Hideo
The Authors Are With The Graduate School Of Information Science Nara Institute Of Science And Techno
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Singh Virendra
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Inoue Michiko
The Authors Are With The Nara Institute Of Science And Technology (naist)
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SALUJA Kewal
The author is with the University of Wisconsin-Madison
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Saluja K
Department Of Electrical And Computer Engineering University Of Wisconsin-madison
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