A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
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概要
- 論文の詳細を見る
This paper presents a broadside test generation method for transition faults in partial scan circuits. In order to generate broadside transition tests for a given partial scan circuit whose kernel circuit is acyclic, this method transforms the kernel circuit into some combinational circuits called broadside test generation models. These models are constructed by using a time-expansion model of the kernel circuit. All the broadside transition tests are generated by performing constrained stuck-at test generation on the broadside test generation models. This method is effective in terms of over-testing as well as area overhead compared with enhanced scan testing and broadside testing based on full scan technique. Experimental results show that the proposed method can alleviate the over-testing issue in reasonable test generation time.
- 社団法人電子情報通信学会の論文
- 2005-11-25
著者
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IWAGAKI Tsuyoshi
School of Information Science, Japan Advanced Institute of Science and Technology
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Fujiwara Hideo
Graduate School Of Information Science Nara Institute Of Science And Technology
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OHTAKE Satoshi
Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
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Fujiwara H
Nara Inst. Of Sci. And Technol. Nara Jpn
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Ohtake Satoshi
Graduate School Of Information Science Nara Institute Of Science And Technology
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Fujiwara Hideo
Graduate School Of Information Of Science Nara Institute Of Science And Technology
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Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
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