Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
スポンサーリンク
概要
- 論文の詳細を見る
- 2011-12-01
著者
-
Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology
-
Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology
-
Iwagaki Tsuyoshi
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
-
TAKEDA Eiri
School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
-
Takeda Eiri
School Of Information Science Japan Advanced Institute Of Science And Technology (jaist)
関連論文
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
- LMS-Based Algorithms with Multi-Band Decomposition of the Estimation Error Applied to System Identification (Special Section on Digital Signal Processing)
- Multi-Band Decomposition of the Linear Prediction Error Applied to Adaptive AR Spectral Estimation
- Adaptive AR Spectral Estimation Based on Wavelet Decomposition of the Linear Prediction Error
- An integer programming formulation for generating high quality transition tests (システムLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis
- An integer programming formulation for generating high quality transition tests (ディペンダブルコンピューティング・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (VLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
- Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems
- A-3-5 A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs
- Characterization and Computation of Steiner Routing Based on Elmore's Delay Model
- A-3-9 Analysis of Fault Coverage under a Power Budget in Scan Testing
- Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
- Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
- A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths
- Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle
- Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation