Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation
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概要
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In recent application-specific integrated circuit design, using transparent latches as storage elements has been intensively studied, since designs using latches (latch-based design) has a large potential to improve the performance yield. However, latch-based design is prone to violate the hold constraint because it is difficult for latches to hold the output data when input switches during the transparent state. To address the hold problem, this paper proposes a novel hold guarantee framework in latch-based design, based on the lifetime extension approach. Since the lifetime extension-based design suffers from an increase in registers due to the strict sharing condition, another method referred to as minimum-delay compensation (MDC) is introduced to accelerate the register sharing. The excessive use of MDC increases the total design cost on the contrary, thereby, this paper formulates the MDC cost (especially, area cost) minimization problem under the specified number of registers, and reveals the computational complexities of the problem. To tackle the problem, two algorithms are proposed: the left-edge-based algorithm and the integer linear programming-based algorithm. They are applied to benchmark circuits, and experimental results showed that the proposed framework can reduce the area cost compared to conventional design with keeping the hold constraint.
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著者
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INOUE Keisuke
School of Information Science, Japan Advanced Institute of Science and Technology
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Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology
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Inoue Keisuke
School Of Information Science Japan Advanced Institute Of Science And Technology
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