A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
スポンサーリンク
概要
- 論文の詳細を見る
A systematic procedure to configure fault-tolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed from a target regular algorithm and the transformation onto physical time-processor domain. The resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While it needs sophisticated connection scheme between processing elements to guarantee the fault-tolerance on communication links, the link complexity is possibly reduced by optimizing redundant operation scheme. Unconstrained and constrained link minimization problems are introduced, and the possibility and the constraints required for link complexity reduction are investigated.
- 社団法人電子情報通信学会の論文
- 1996-12-25
著者
-
KANEKO Mineo
School of Information Science, Japan Advanced Institute of Science and Technology
-
Kaneko M
Japan Advanced Inst. Sci. And Technol. Ishikawa‐ken Jpn
-
Kaneko Mineo
School Of Information Science Japan Advanced Institute Of Science And Technology
-
MIYAUCHI Hiroyuki
Department of Chemical Engineering, Graduate School of Engineering, Tohoku University
-
Miyauchi Hiroyuki
Department Of Chemical Engineering Graduate School Of Engineering Tohoku University
関連論文
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
- Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
- Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
- Fabrication of Mono- and Multi-Layers of Submicron-Sized Spheres by a Dip-Coating Technique and Their Transmittance Property
- LMS-Based Algorithms with Multi-Band Decomposition of the Estimation Error Applied to System Identification (Special Section on Digital Signal Processing)
- Multi-Band Decomposition of the Linear Prediction Error Applied to Adaptive AR Spectral Estimation
- Adaptive AR Spectral Estimation Based on Wavelet Decomposition of the Linear Prediction Error
- An integer programming formulation for generating high quality transition tests (システムLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis
- An integer programming formulation for generating high quality transition tests (ディペンダブルコンピューティング・デザインガイア2008--VLSI設計の新しい大地)
- An integer programming formulation for generating high quality transition tests (VLSI設計技術・デザインガイア2008--VLSI設計の新しい大地)
- A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
- Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems
- A-3-5 A Heuristic Approach to Detecting Transition Faults at All Circuit Outputs
- Characterization and Computation of Steiner Routing Based on Elmore's Delay Model
- Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
- Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
- A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths
- Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle
- Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation