Fujiwara Hideo | Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

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概要

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著作論文

Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
D-10-18 An Approach to Temperature Control During VLSI Test
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
Scheduling Power-Constrained Tests through the SoC Functional Bus
NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (信号処理)
Effect of BIST Pretest on IC Defect Level(Dependable Computing)
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)
A Low Power Deterministic Test Using Scan Chain Disable Technique

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